1. Field of the Invention
The present invention relates to apparatus for alignment and positioning of a semiconductor wafer in the testing of integrated circuit chips on the wafer, and in particular to wafer alignment and positioning apparatus used in testing of a chip by observation with voltage contrast electron microscopy while the chip circuits are powered through electrical probe contacts.
2. Description of Related Art
An integrated circuit (or IC) is a complete electronic circuit containing transistors and perhaps diodes, resistors, and capacitors together with their electrical interconnections, processed on and contained completely within a single chip of silicon. The size of the chip is typically on the order of 1/16th inch square. The advantages of such small size include the possibility of building extremely complicated systems such as powerful digital computers which are very compact. Small circuits not only require less space but less power as well, so that power supplies and cooling equipment can also be correspongingly smaller and less expensive. The cost savings from the use of ICs are not just those derived from their smaller size, however. A large part of their economy stems from the decreased manufacturing cost of the circuits themselves. The cost of processing a semiconductor chip is roughly proportional to its area, whether it holds a single transistor or a complex IC, because roughly the same number of manufacturing steps are involved in producing a wafer. By packing more components into a smaller chip area, the cost per component is reduced. An additional saving lies in the fact that the use of IC building blocks translates into fewer parts to order, inventory, and assemble into a given system.
In addition to all the advantages of small size and low cost, there is also the enormous advantage of much better reliability--the fact that a circuit or system can perform for a long time without degradation of performance or breakdowns. IC systems are much less inclined to fail than discrete versions of the same system. The most important reason for this is that IC systems require significantly fewer solder joints and mechanical connections, and these account for most failures in a solid-state system. Furthermore, because the use of ICs means fewer separately assembled components, there is a smaller chance of mistakes being made in assembly, or of faulty components being used.
The manufacture of IC chips starts with a wafer cut from a single crystal of a semiconductor such as silicon. Numerous chips are fabricated on the wafer at one time, and the wafer is then cut up into its separate chips. In a typical manufacturing process, successive diffusions of dopants are made through appropriately shaped windows etched in the oxide layer by an acid. After each diffusion, the set of windows is covered by growing a new oxide layer, and after a final set of windows is etched, a layer of gold or aluminum metallization is deposited over the oxide. An acid is again used to eat away all but certain desired strips and squares of the metal to leave a pattern of electrical leads and large bonding pad areas at the ends of some leads. Fine gold wires are attached during the assembly process, after a chip has been cut from the wafer. After assembly each individual IC is put through many tests of its electrical performance to ensure that it meets specifications.
It is advantageous to be able to test chips while they are still on the wafer, before the gold wires are attached to the bonding pads, so that defective chips are culled before bonding takes place. Wafers are generally tested on an automatic test system that applies test patterns to the chip through probes. Commercial wafer test probes are manufactured which allow metal probe fingers to connect mechanically to any particular chip on a semiconductor wafer and which allow electrical tests to be made on that chip. The time required to apply a sufficiently large number of test stimuli to determine that the chip under test is functioning correctly can have an important effect on the cost of the final product.
Another way to test a semiconductor chip which provides additional information is to examine the chip while the circuits of the chip are operating with a scanning electron microscope equipped with a voltage contrast detector. The rate of secondary electron emission varies with the voltage at a given area, and this variation is converted into contrast variation in the readout mechanism, such as a television monitor screen. This method of testing allows observation of voltages at any point in the chip, not just at the points which are connected to mechanical probes or bond wires.
Not all of a very large VLSI chip can be seen at one time in a scanning electron microscope. In order to observe different parts of the chip with a secondary electron detector while the circuits of the chip are powered through mechanical probes, it is necessary in the present state of the art to lift the mechanical probes off the wafer, reposition the wafer, realign the probes with the wafer, and lower the probes into contact with the wafer. This process must be repeated each time a different portion of the chip is looked at. Such a time-consuming procedure makes it impractical to test IC chips routinely in this way.